1. Field of the Invention
This invention relates to a semiconductor memory device into which data can be electrically written and from which data can be electrically erased. In particular, this invention relates to a semiconductor memory device wherein the data stored in all memory cells can be erased simultaneously.
2. Description of the Related Art
A flash type electrical erasable programmable read only memory (FE.sup.2 PROM) with a function to electrically erase all of the stored bits in a simultaneous manner is known as disclosed in U.S. Pat. Nos. 4,437,172 and 4,466,081. The FE.sup.2 PROM as disclosed in these patents allows the stored data to be electrically and simultaneously erased on all of the bit lines. With this advantageous feature, the FE.sup.2 PROM has progressively superseded the UV type EPROM in which the data stored therein is erased by ultraviolet rays.
An example of one of the memory cells constituting the FE.sup.2 PROM is illustrated in cross sectional form in FIG. 1.
In FIG. 1, showing the structure of the conventional memory cell, reference numeral 30 designates a p-type semiconductor substrate. Field oxide film 31 is layered on substrate 30, and erase gate 32, acting as a first polysilicon layer, is partially layered on field oxidation film 31. Reference numeral 33 indicates a gate oxide film. Floating gate 34 is layered on gate oxide film 33, and consists of a second polysilicon layer. The end portion of floating gate 34 is overlaid on the end portion of erase gate 32, with silicon oxide film 35 interlayered between them. Silicon oxide film 35 serves as an insulating film and is formed by oxidizing erase gate 32. Control gate 37, which serves as a third polysilicon layer, is layered over floating gate 34, with silicon oxide film 36 interlayered between them. Silicon oxide film 36 serves as an insulating film and is formed by oxidizing floating gate 34. Although not shown, source and drain regions as N type diffusion layers are provided on substrate 30, and located at sides of floating gate 34, respectively. An interlayer insulating film (not shown) is layered on control gate 37, and has contact holes opened to the source and drain regions, and the surfaces of erase gate 32 and control gate 37. Within each contact hole is formed a lead electrode made of aluminum.
The data write operation of the FE.sup.2 PROM with the memory cells thus structured is similar to that of a conventional EPROM. Specifically, a high voltage is applied to the drain region (not shown) of the memory cell, and control gate 37. The applied high voltage generates hot electrons in the channel region located under floating gate 34. The generated hot electrons are injected into the floating gate 34 as set at a predetermined potential, because the high voltage has been applied to control gate 37. The injection of electrons into floating gate 34 increases the threshold voltage in the channel region.
In an erasure mode, for erasing the data, a high voltage is applied to erase gate 32, to place the silicon oxide film 35 between erase gate 32 and floating gate 34 in a high electric field. Under this condition, the electrons which have been already injected into floating gate 34, are discharged into erase gate 32. As the result of this discharge, the threshold voltage in the channel region decreases, and the data is erased.
In a read mode for reading out the data, a fixed voltage is applied to the drain region and control gate 37. Under this condition, the memory cells into which the data have been written and whose channel regions have increased threshold voltage, are in an off state. Those memory cells whose data has been erased and whose channel regions have decreased threshold voltages, are in an on state. The on- and off-states are read out in the form of logical "1" and "0", respectively.
In the memory cell as mentioned above, for data erasure, electrons are discharged through silicon oxide film 35 to erase gate 32, from floating gate 34. Therefore, the erasure characteristic of this cell depends on the quality and thickness of silicon oxide film 35, and the shapes of floating gate 34 and erase gate 32, which are separated by silicon oxide film 35. To quicken the erasure operation, for example, silicon oxide film 35 is thin. Silicon oxide film 35 is reduced by appropriately selecting a way of process for erase gate 32 and a method of forming silicon oxide film 35. However, it is very difficult to appropriately select the process and formation. If the selection is inappropriate, the data write and erasure may be performed erroneously or more adversely silicon oxide film 35 may be electrically broken down. Thus, great care must be used for such selection.
In FE.sup.2 PROM, the cause for erroneous data write has been known and will be described. In the write mode, a high voltage is applied to control gate 37 and the drain. The same substrate further contains other memory cells which are not in the write mode, but whose control gates 37 are applied with the same high voltage. In those other memory cells, the potential at floating gate 34 is pulled to a high potential level, so that an electric field is developed between floating gate 34 and erase gate 32. It has been known that an irregularity, called asperity, is inevitably formed on the upper surface of a polysilicon layer. The leak current flowing from the first polysilicon layer having a surface of small asperity to the second polysilicon layer having a surface of great asperity is larger than the leak current flowing from the second polysilicon layer to the first polysilicon layer. In other words, more electrons move from the second to the first polysilicon layer than the first to the second polysilicon layer. In the case of the FIG. 1 memory cell, the asperity on the upper surface of erase gate 32 is larger than that on the lower surface of floating gate 34. Therefore, electrons may be injected into floating gate 34, through silicon oxide film 35 existing between erase gate 32 and floating gate 34. In this way, the erroneous data write is caused by injecting electrons into the floating gates of those memory cells which are not in the write mode.
An ideal characteristic required for the insulating films used in the memory cells in FE.sup.2 PROM is that the leak current easily flows in the erasure direction, but hardly flows in the opposite direction, i.e., the write direction. In this respect, the electrical characteristic of the conventional memory cell shown in FIG. 1 is not always satisfactory.
To cope with this, the memory cell as shown in sectional form in FIG. 2 has been proposed. In this memory cell, the first polysilicon layer constitutes floating gate 34. A second polysilicon layer forms an erase gate 32. Insulating film 38 existing between erase gate 32 and control gate 37 is formed by oxidizing the polysilicon of erase gate 32.
In the FIG. 2 prior art, one end portion of erase gate 32 is laid on the end portion of floating gate 34. Therefore, a relative large asperity is formed on the upper surface of floating gate 34. At this time, more electrons move from the lower surface of erase gate 32 having a surface of small asperity to the upper surface of floating gate 34 having a surface of great asperity than from the upper surface of floating gate 34 to the lower surface of erase gate 32. Therefore, in the memory cell of FIG. 2, the erroneous write operation is restricted and the erasure characteristic is improved.
In the FIG. 2 memory cell as well as the FIG. 1 memory cell, erase gate 32 and control gate 37 are used to conductive layer respectively. For the resistance reduction purpose, the polysilicon layers constituting the erase gate and the control gate are doped with impurity, for example, phosphorus atoms or arsenic atoms at 6.times.10.sup.20 /cm.sup.3 or more of concentration, viz., at a concentration of the solution limit. Similarly, the polysilicon layer forming floating gate 34 is doped with phosphorus atoms or arsenic atoms at a concentration of the solution limit. Therefore, a degree of asperity occurring on the upper surface of floating gate 34 is small. A leak current caused between floating gate 34 and erase gate 32 in the erroneous write direction is nearly equal to that in the erasure direction. In this respect, the erroneous write characteristic and the erasure characteristic are both improved unsatisfactorily.